Chemical mechanical polishing (CMP) is an established semiconductor manufacturing process step. CMP has been widely employed in the manufacture of semiconductor devices to eliminate topographic variations and accomplish global planarization of wafer surfaces. Particulate surface contamination of semiconductor wafers after the CMP process is a serious problem that affects yield in the industry. Micrometer and sub-micrometer particle removal from the device feature surfaces is related to high productivity, low cost-of-ownership manufacturing. For more than 30 years the semiconductor industry has upheld Moore's Law, i.e., the theory that computational power will double every 18 months, largely because decreases in device feature sizes have produced increases in the operational speed of logic devices and corresponding reductions in production costs—and sustained the historical rate of cost reduction of new semiconductor products. Continued reduction in feature sizes has driven more stringent performance requirements for every step in the manufacture of integrated circuits, including the post-CMP cleaning step. Post-CMP cleaning is a process to minimize particles and other contaminants that come from various sources in the CMP process. In the semiconductor industry, during the early development of the CMP and cleaning processes, the two processes were evaluated independently of one another. Under the current paradigm, the CMP and post-CMP cleaning processes are interrelated and the performance of a post-CMP cleaning process is related to high productivity and low production costs.
When device feature sizes shrink to less than 0.18 μm, the complexity of interconnect structures becomes a significant factor affecting integrated circuit design and performance. As semiconductor device feature sizes decrease with advancing technologies, there is a need for effective post-CMP cleaning methods to remove CMP residue and reduce particulate contamination to acceptable levels, e.g., <1013 atoms/cm2.
In recent years, as the semiconductor industry approached the 180-nm technology node (Ref.: International Technology Roadmap for Semiconductors (ITRS) 1999, laying out a 15-year outlook for the industry), the performance limitations of aluminum and silicon interconnects presented challenges to industry efforts to sustain Moore's Law. In general, interconnection delays have been found to increase with the square of the reduction in feature size. As device geometries shrink, more emphasis must be placed on the interconnect structures to minimize resistance-capacitance time delays. One approach to minimizing interconnection delays has been to add more layers of metal. Adding more layers of metal, however, has the disadvantages of increasing production costs and generating additional heat, with adverse effect on device performance and reliability.
Strategies to minimize interconnect delays include improving conductivity and lowering the dielectric constant (k) value by employing low-k films. For example, copper (Cu) has emerged as a replacement for conventional aluminum (Al) as the interconnect metal in advanced devices. Copper has greater conductivity than aluminum (thus reducing resistance-capacitance time delays) and also is less subject to electromigration when compared to conventional Al metallization. The material properties of Cu present challenges to the CMP and post-CMP cleaning processes. One challenge in Cu CMP is minimizing the formation of micro-scratches (a common problem in CMP processes), which can degrade device performance. Copper is softer than other materials such as tungsten and thus scratches more easily. Other challenges include the problems of dishing, erosion, and thinning of Cu lines beyond the target thickness that can generate increased line resistance and resistance-capacitance time delays—all of which are due to the relative softness of Cu metal. There is a need for post-CMP cleaning methods to remove residual slurry particles (CMP slurry is a mix of liquids and abrasive powder) with complex compositions, pieces of polishing pad used in CMP, and copper contamination such as trace levels of Cu metal ions.
The adhesion of slurry particles and Cu metal ions to wafers is a problem in post-CMP cleaning processes. Adhesion forces, which can be a combination of bonding forces such as long range van der Waals forces, chemical or hydrogen bonds, and electrostatic forces, are responsible for the adhesion of particles on the surface of the wafer. There is a need for post-CMP cleaning methods that are capable of overcoming these forces.
Additionally, tendency of Cu to diffuse into underlying substrates such as silicon makes the use of diffusion barrier materials, such as tantalum (Ta)- and tungsten (W)-based diffusion barrier materials, a necessity. Effective CMP of Cu structures requires removal of both the Cu and barrier layers. Barrier materials are typically more difficult than Cu to planarize using conventional slurries (conventional slurries contain a single type of abrasive), which necessitates tailoring slurries to the characteristics of Cu and the Ta- and W-based barrier materials. After the CMP process, a large quantity of slurry particles, along with pieces of polishing pad, metal contaminants, and diffusion barrier material remaining on the device's surface must be removed. There is a need for effective post-CMP cleaning methods that are independent of the film materials.
The emergence of dual-damascene processing (techniques for the simultaneous formation of a conductive plug in electrical contact with a conductive line) includes developing processes that are highly flexible, including those for CMP and post-CMP cleaning. Dual-damascene processing of copper for the patterning of Cu metal into interconnect structures that also include low-k dielectric materials presents still additional challenges, because of the lower density, inferior mechanical properties, and typically increased organic content of low-k materials.
Post-CMP cleaning has become a challenging cleaning application in semiconductor manufacturing. Effective post-CMP cleaning processes are needed to ensure that the challenges of replacing Al metallization with Cu dual-damascene structures, integrating Cu and low-k materials, along with decreasing device feature sizes, and the transition to 300-mm size wafers, are met. There is a need for effective post-CMP cleaning processes to achieve improved device performance with higher productivity and reduced production costs.
The current post-CMP cleaning practices include non-contact cleaning using megasonic baths and contact cleaning using brush scrubbers. The brush (contact) cleaning methods are based on a direct contact between a brush and the wafer surface. Brush cleaning requires that the wafer surface be mechanically washed or brushed by a commercially available equipment called a scrubber. The scrubber may employ heat or ultrasonic augmentation and typically requires immersion times of two to twenty minutes to achieve complete removal of the CMP residue from the wafer surface. While high brush pressure is desirable for the purposes of increasing the contact between the particle and the brush to a point where the adhesion forces can be overcome, high pressure above a certain point can contribute to scratching of the wafer surface by the removed particle. In practice, brush cleaning effectiveness depends on the brush pressure and speed, rate of flow of cleaning solution, and cleaning time. Megasonic (non-contact) cleaning uses high-frequency acoustic pressure waves to remove particles from the wafer surface. Megasonic cleaning effectiveness depends on the megasonic intensity, solution temperature, chemistry, and cleaning time.
It is well known that particulate surface contamination of semiconductor wafers after the CMP process degrades device performance and affects yield in the industry. Additionally, it is well known that the cost of manufacturing a semiconductor is proportional to the time employed for each processing step. It would be advantageous to be able to remove the CMP residue and contaminants without using the mechanical washing or brushing employed by the scrubber in order to reduce an amount of the defects and the scratches. Further, it would be advantageous to more effectively remove the CMP residue and contaminants from the surface features on the wafer surface.
What is needed is an effective post-CMP cleaning method to remove the CMP process residue and contaminants that does not use the mechanical washing, brushing or megasonic baths.
What is further needed is a method of removing the CMP residue and contaminants from the surface features that is more effective than the current post-CMP cleaning methods including mechanical washing, brushing, or megasonic cleaning.
What is additionally needed is a post-CMP cleaning method to achieve improved device performance with higher productivity and reduced production costs.